Oriental Hydrocyphon (Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India

Oriental Hydrocyphon (Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India

Blog Article

Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom.Accurate and rapid simulation tools are needed to explore the design space.To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator.

However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated.The work presented in this paper aims at mitigating this overhead, exploiting a form of read more software-driven platform runtime reconfiguration.We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation.

The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel.Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical nightstick twm-850xl modeling to extract area and power/energy consumption figures.We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.

5% in terms of operating frequency.